The DAC8554IPW is a 16-bit, quad-channel, voltage output, digital-to-analog converter (DAC), offering low-power operation and a flexible serial host interface. It offers monotonicity, good linearity, and exceptionally low glitch. Each on-chip precision output amplifier allows rail-to-rail output swing to be achieved over the supply range of 2.7V to 5.5V. The device supports a standard 3-wire serial interface capable of operating with input data clock frequencies up to 50MHz for IOVDD = 5V.
The DAC8554IPW requires an external reference voltage to set the output range of each DAC channel. Also incorporated into the device is a power-on reset circuit which ensures that the DAC outputs power up at zero-scale and remain there until a valid write takes place. The DAC8554IPW provides a per channel power-down feature, accessed over the serial interface, that reduces the current consumption to 175nA per channel at 5V.
The low-power consumption of this device in normal operation makes it ideally suited to portable battery-operated equipment and other low-power applications. The power consumption is 4.25mW at 5V, reducing to 4µW in power-down mode.
The DAC8554IPW is available in a TSSOP-16 package with a specified operating temperature range of -40°C to +105°C.
Feature
Relative Accuracy: 4LSB
Glitch Energy: 0.15nV-s
MicroPower Operation: 150µA per channel at 2.7V
Power-On Reset to Zero-Scale
Power Supply: +2.7V to +5.5V
16-Bit Monotonic Over Temperature
Settling Time: 10µs to ±0.003%FSR
Ultra-Low AC Crosstalk: -100dB Typ
Low Power SPI Compatible Serial Interface with Schmitt-Triggered Inputs: Up to 50MHz
On-Chip Output Buffer Amplifier with Rail-to-Rail Operation
Double Buffered Input Architecture
Simultaneous or Sequential Output Update and Power-Down
16-Channel Broadcast Capability
1.8V to 5.5V Logic Compatibility
Available in a TSSOP-16 Package
APPLICATIONS
Catalogue
FPGA / CPLD
Memory
MOS 
MCU 
DSP
OCEP
Secondary 
Other 
