• 3-state parallel outputs for connection to common bus

• Separate serial outputs synchronous to both positive and negative clock edges for cascading

• Medium speed operation - 5 MHz at 10 V (typ.)

• Standardized, symmetrical output characteristics

• 100% tested for quiescent current at 20 V

• Maximum input current of 1 μA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C

• Noise margin (full package temperature range): 1 V at VDD = 5 V 2 V at VDD = 10 V 2.5 V at VDD = 15 V

• 5-V, 10-V, and 15-V parametric ratings

• Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"

• Applications

• Serial-to-parallel data conversion

• Remote control holding register

• Dual-rank shift, hold, and bus applications

CD4094B is an 8-stage serial shift register having a storage latch associated with each stage for strobingdata from the serial input to parallel buffered 3-state outputs. The parallel outputs may be connected directly to common bus lines. Data is shifted on positive clock transitions. The data in each shift register stage is transferred to the storage register when the STROBE input is high. Data in the storage register appears at the outputs whenever the OUTPUT-ENABLE signal is high.

Two serial outputs are available for cascading a number of CD4094B devices. Data is available at the QS serial output terminal on positive clock edges to allow for high-speed operation in cascaded systems in which the clock rise time is fast. The same serial information, available at the Q'S terminal on the next negative clock edge, provides a means for cascading CD4094B devices when the clock rise time is slow.

The CD4094B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).