All trademarks are the property of their respective owners.
Description
The SNx4HC273 devices are positive-edge-triggered D-type flip-flops with a direct active low clear (CLR) input.
Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not related directly to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output.
Feature
Wide Operating Voltage Range of 2 V to 6 V
Outputs Can Drive Up to 10 LSTTL Loads
Low Power Consumption, 80-μA Maximum ICC
Typical tpd = 12 ns
±4-mA Output Drive at 5 V
Low Input Current of 1-μA Maximum
Contain Eight Flip-Flops With Single-Rail Outputs
Direct Clear Input
Individual Data Input to Each Flip-Flop
On Products Compliant to MIL-PRF-38535,All Parameters Are Tested Unless Otherwise Noted. On All Other Products, Production Processing Does Not Necessarily Include Testing of All Parameters.
All trademarks are the property of their respective owners.
Description
The SNx4HC273 devices are positive-edge-triggered D-type flip-flops with a direct active low clear (CLR) input.
Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not related directly to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output.
Catalogue
FPGA / CPLD
Memory
MOS 
MCU 
DSP
OCEP
Secondary 
Other 
