Fabricated using the revolutionary, complementary Silicon-Germanium (SiGe) BiCom3X process, the THS7372IPWR is a low-power, single-supply, 2.7-V to 5-V, four-channel integrated video buffer. It incorporates one SDTV filter and three fixed Full-HD (also known as True-HD) HDTV filters. All filters feature sixth-order Butterworth characteristics that are useful as digital-to-analog converter (DAC) reconstruction filters or as analog-to-digital converter (ADC) anti-aliasing filters.
The THS7372IPWR has flexible input coupling capabilities, and can be configured for either ac- or dc-coupled inputs. The 300-mV output level shift allows for a full sync dynamic range at the output with 0-V input. AC-coupled modes include a transparent sync-tip clamp for CVBS, Y’, and G’B’R’ signals. AC-coupled biasing for P’B/P’R channels can easily be achieved by adding an external resistor to VS+.
The THS7372IPWR is an ideal choice for a wide range of video buffer applications. Its rail-to-rail output stage with 6-dB gain allows for both ac and dc line driving. The ability to drive two lines, or 75-Ω loads, allows for maximum flexibility as a video line driver. The 23.4-mA total quiescent current at 3.3 V and 0.1 μA (disabled mode) makes it well-suited for systems that must meet power-sensitive Energy Star? standards.
The THS7372IPWR is available in a TSSOP-14 package that is lead-free and green (RoHS-compliant).
Feature
One SDTV Video Amplifier for CVBS Video
Three Fixed Full-HD 1080p60 Filters for Y’/P’B/P’R, G’B’R’, or Computer RGB Outputs
Sixth-Order Low-Pass Filters:
Versatile Input Biasing:
Built-in 6-dB Gain (2 V/V)
+2.7-V to +5-V Single-Supply Operation
Rail-to-Rail Output:
Low Total Quiescent Current: 23.4 mA at 3.3 V
Disabled Supply Current Function: 0.1 μA
Low Differential Gain/Phase: 0.2%/0.35°
RoHS-Compliant TSSOP-14 Package
Catalogue
FPGA / CPLD
Memory
MOS 
MCU 
DSP
OCEP
Secondary 
Other 
