MAX 3000A devices are low–cost, high–performance devices based on the Altera MAX architecture. Fabricated with advanced CMOS technology, the EEPROM–based MAX 3000A devices operate with a 3.3-V supply voltage and provide 600 to 10,000 usable gates, ISP, pin-to-pin delays as fast as 4.5 ns, and counter speeds of up to 227.3 MHz.
Feature
■ High–performance, low–cost CMOS EEPROM–based programmable logic devices (PLDs) built on a MAX® architecture (see Table 1)
■ 3.3-V in-system programmability (ISP) through the built–in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability
– ISP circuitry compliant with IEEE Std. 1532
■ Built–in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990
■ Enhanced ISP features:
– Enhanced ISP algorithm for faster programming
– ISP_Done bit to ensure complete programming
– Pull-up resistor on I/O pins during in–system programming
The EPM3064ATC100-4N is a programmable logic device (CPLD) from Intel / Altera, belonging to the MAX 3000A series. With 64 macrocells and 66 I/O's, it offers medium-density and high-performance programmable logic solutions. Housed in a TQFP-100 package, it has a maximum frequency of 222.2MHz, a propagation delay of 4.5ns, and operates within a supply voltage range of 3V - 3.6V. Ideal for applications in industrial control, communications, and consumer electronics, it supports in-system programmability and JTAG boundary-scan test.
Benefits
High-performance, low-cost CMOS EEPROM-based programmable logic device
3.3-V in-system programmability through IEEE Std 1149.1 JTAG interface
Built-in boundary-scan test circuitry compliant with IEEE Std 1149.1-1990
Enhanced ISP features for faster programming
Flexible and reprogrammable logic functions
Medium-density with 64 macrocells and 66 I/O's
Application Examples
Catalogue
FPGA / CPLD
Memory
MOS 
MCU 
DSP
OCEP
Secondary 
Other 
