Compliant to USB specification Revision 2.0
− 4 downstream ports
− Upstream port supports both high-speed (HS) and full-speed (FS) traffic
− Downstream ports support HS, FS, and low-speed (LS) traffic
− 1 control pipe (endpoint 0, 64-byte data payload) and 1 interrupt pipe (endpoint 1, 1-byte data
payload)
− Backward compatible to USB specification Revision 1.1
Catalogue
FPGA / CPLD
Memory
MOS 
MCU 
DSP
OCEP
Secondary 
Other 
