The ZL30161GDG2 is a single channel Network Synchronization Clock Translator combining a single DPLL / NCO with three programmable synthesizers. The device is a fully compliant SEC (G.813) and EEC (G.8262) flexible rate conversion DPLL. It is capable of accepting and generating any frequency from 1Hz to 750MHz on up to eleven input references and up to twelve output clocks.Key
Feature
Fully compliant SEC (G.813) and EEC (G.8262) flexible rate conversion Digital Phase Locked Loop (DPLL)
Programmable digital PLL/Numerically Controlled Oscillator (NCO) synchronizes to any clock rate from 1Hz to 750MHz
Three programmable synthesizers generate any clock rate from 1Hz to 750MHz with maximum jitter below 0.62 ps rms
Flexible two-stage architecture translates between arbitrary data rates, line coding rates and FEC rates
Digital PLLs filter jitter from 0.1mHz up to 1kHz
Programmable DPLL can synchronize to sync pulse and sync pulse/clock pair
Automatic hitless reference switching and digital holdover on reference fail
Reference inputs:
Any Output Frequency:
Six LVPECL output clocks
Six LVCMOS output clocks
Up to four unique customer defined default configurations, including input/output frequencies, are available via OTP (One Time Programmable) memory
Easy Configuration and dynamic programming via SPI/I2C interface
Operates from a single crystal resonator or clock oscillator