I What is a Logic Gate?

Electronic circuits that implement basic and common logic operations are called logic gate circuits. The gate implementing AND operation is AND gate, that implementing OR operation is OR gate, and that implementing NOT operation is NOT gate, also called inverter gate, etc.. (Logic 1 represents high level; logic 0 represents low level)

1. AND Gate

Logical expression: F=A∙B

Only when the input terminals A and B are both 1, the output terminal Y is 1, otherwise, Y is 0. Common chip models of AND gates are: 74LS08, 74LS09, etc.

AND Truth Table

2. OR Gate

Logical expression: F=A+B

When one of the input terminals A and B is 1, the output terminal Y is 1; when the input terminals A and B are both 0, Y will be 0. Common chip models of OR gates are: 74LS32, etc.

OR Truth Table

3. NOT Gate

Logical expression: F=A'

The output terminal is always opposite to the input terminal. Common chip models of NOT gates are: 74LS04, 74LS05, 74LS06, 74LS14, etc.

NOT Truth Table

4. NAND Gate

Logical expression: F=A'B'

That is, only when all input terminals A and B are 1, the output terminal Y is 0, otherwise, Y is 1. Common chip models of NAND gates are: 74LS00, 74LS03, 74S31, 74LS132, etc.

The NAND symbol:

NAND Truth Table

5. NOR Gate

Logical expression: F=A'+B'

As long as one of the input terminals A and B is 1, the output terminal Y is 0. When the input terminals A and B are both 0, Y will be 1. Common chip models of NOR gates are: 74LS02, etc.

NOR Truth Table

6. XNOR Gate

Logical expression: F=A∙B+A'B'

XNOR Truth Table

7. XOR Gate

Logical expression: F=A∙'B+A∙B'

XOR symbol:

XOR Truth Table

8. AND-OR-NOT Gate

Logical expression: F=A'B'+C'D'

AND-OR-NOT Truth Table

II RS Flip-flop

1. Circuit Structure

Connect the input and output ends of the two NAND gates G1 and G2 to form a basic RS flip-flop. The logic circuit is shown in the Figure below. It has two input terminals R and S and two output terminals Q and Q'

Figure 1.Basic RS flip-flop Simple Circuits Diagrams Consist of 2 NAND Gates

The logic equation of the basic RS flip-flop is:

According to the two formulas, the relationship between its four inputs and outputs is:

(1) When R=1, S=0, then Q=0, Q'=1, and the flip-flop is set to 1.

(2) When R=0, S=1, then Q=1, Q'=0, and the flip-flop is set to 0.

When two input terminals of the flip-flop are added with different logic levels, its two output terminals Q and Q' have two complementary stable states. Generally, and the state of the terminal Q is defined as the state of the flip-flop.

When Q=1 and Q'=0, the flip-flop is set to in 1, otherwise, the flip-flop is set to 0.

When S=0, R=1, the flip-flop is set to 1. Since the decision condition for the setting is S=0, the S terminal is called the set 1 terminal.

When R=0, S=1, the flip-flop is set to 0, called reset.

In the same way, the R terminal is called the set 0 terminal or the reset terminal. If the flip-flop is in the 1 state, and you want to change it to the 0 state, you must change the level of the R terminal from 1 to 0, and the level of the S terminal from 0 to 1.

The input signal (low level) added here is called the trigger signal, and the conversion process caused by them is called flip. Because the trigger signal here is level, this kind of trigger is called the level control trigger.

From a functional point of view, it can only be set to 0 and 1 under the action of S and R, so it is also called a set to 0 or reset flip-flop. The logic symbol is shown in Figure 1(b). Since setting 0 or 1 is valid only when the trigger signal is low level, therefore, the S end and R end are drawn with small circles

(3) When terminal R and S are all invalid, the trigger state remains unchanged.

When the flip-flop state remains unchanged, the input terminals are all added with an invalid level (high level). When a flip is required, a negative pulse must be added to one input terminal. For example, when you add a negative pulse to the S terminal to set the trigger to 1, after it returns to the high level, the flip-flop remains in the 1 state. This is equivalent to storing the level signal at a certain moment in the S terminal, which reflects the memory function of the flip-flop.

(4) When the R and S end are all valid, the trigger state is uncertain.

Under this condition, the output terminals Q and Q' of the two NAND gates are both 1. After both input signals are removed at the same time (back to 1), because the delay time of the two NAND gates cannot be determined, it's not sure whether the flip-flop state is 1 or 0. This situation is called an indeterminate state, which should be avoided.

In other words, because the terminal R and S can be set to 0 and 1 at a low level, the two cannot be 0 at the same time.

Figure 2..Basic RS flip-flop Consists of 2 NOR Gates

2. Characteristic Equation

3. Features

(1) The basic RS flip-flop has the functions of setting, resetting, and maintain (memory);

(2) The trigger signal of the basic RS trigger is valid at a low level, which belongs to the level trigger mode;

(3) The basic RS flip-flop has constraints (R+S=1), because the delay time of the two NAND gates cannot be determined, when R=S=0, the next state will be uncertain.

(4) It has a poor anti-interference performance. When the input signal changes, the output will change immediately.

III TTL Logic Gate Circuit

A circuit with a bipolar semiconductor as the basic element, integrated on a silicon chip, with certain logic functions is called a bipolar logic integrated circuit, or TTL logic gate circuit. It is a kind of logic gate circuit commonly used in digital electronics, which has been applied earlier and is relatively mature.

TTL is mainly composed of a BJT (bipolar junction transistora>) and a resistor. It has a fast speed. The earliest TTL gate circuit was the 74 series, and then the 74H series, 74L series, 74LS, 74AS, 74ALS and other series appeared. However, because TTL has large power consumption, it is gradually replaced by CMOS circuits.

IV CMOS Logic Gate Circuit

1. TTL VS. CMOS

CMOS logic gate circuit is the second widely used digital integrated device developed after the advent of the TTL circuit. With the improvement of the manufacturing process, the performance of the CMOS circuit may surpass TTL and CMOS may become the dominant logic device.

The working speed of the CMOS circuit can be compared with TTL, and its performance in power consumption and anti-interference are much better than TTL.

In addition, almost all ultra-large-scale storage devices and PLD devices are manufactured using CMOS technology, and the cost is relatively low.

The CMOS gate circuit produced in the early stage was the 4000 series, which was subsequently developed into the 4000B series. CMO devices currently compatible with TTL, such as 74HCT series, can be exchanged with TTL devices.

Let's discuss the CMOS inverter first, and then introduce other CMO logic gate circuits.

2. CMOS Inverter

There are two types of MOSFETs: P-channel and N-channel, and there are depletion and enhancement type in each. The circuit composed of N-channel and P-channel MOSFETs is called a complementary MOS or CMOS circuit.

The following figure shows the CMOS inverter circuit, which consists of two enhancement-mode MOSFETs. One MOSFET has an N-channel structure and the other has a P-channel structure. In order for the circuit to work normally, the power supply voltage VDD is required to be greater than the sum of the absolute values of the two transistors' turn-on voltages: VDD>(VTN+|VTP|).

Figure 1. CMOS Inverter Circuit

(1) Working Principles of Logic

First, consider two limit cases:

when Vl is at 0, the corresponding voltage is approximately 0V;

when Vl is at 1, the corresponding voltage is approximately VDD.

In the two cases, we can assume that the N-channel transistor TN is the working transistor and the P-channel transistor TP is the load transistor. However, since the circuit is complementary and symmetrical, this assumption can be arbitrary, and the opposite situation will lead to the same result.

The following figure analyzes the working condition when Vl=VDD. Add a load line on the output characteristic iD-VDS (VGSN=VDD) of TN (note that VDSN=VO), which is the output characteristic iD-VSD of the load transistor TP when VSGP=0V.

Since VSGP<VT (VTN=|VTP|=VT), the load curve is almost a horizontal line overlapping the horizontal axis. The intersection of the two curves is the operating point.

Obviously, the output voltage at this time VOL≈0V. Generally, this value is less than 10mV, and the current through the two transistors is close to zero. So we can say the power consumption of the circuit is very small (in the order of microwatts)

Figure 2. vI=VDD

The following figure analyzes another limit case, where VI=0V.

At this time, the transistor TN is used when VGSN=0 and its output characteristic iD-VDS almost overlaps the horizontal axis. The load curve is the output characteristic iD-VDS of the load transistor TP when vSGP=VDD. In the figure, the operating point determines VO=VOH≈VDD, and the current through the two devices is close to zero.

The power consumption in the above two limit cases is very low, so the basic CMOS inverter is almost an ideal logic unit. Its output voltage is close to zero or +VDD, and the power consumption is almost zero.

Figure 3. vI＝0V

(2) Transmission Characteristics

The following figure shows the transmission characteristics of a CMOS inverter. In the figure, VDD=10V, VTN=|VTP|=VT=2V. Since VDD>(VTN+|VTP|), when VDD-|VTP|>VI>VTN, both TN, and TP are turned on at the same time. Considering that the circuit is complementary and symmetrical, one device can be the drain load of the other device.

It should also be noted that the device exhibits constant current characteristics in the amplification region (saturation region), and one device can be used as a high-resistance load. Therefore, in the transition area, the transmission characteristics change sharply. The two transistors switch states when VI=VDD/2.

Figure 4. Transmission Characteristics of a CMOS Inverter

(3) Working Speed

When the CMOS inverter under a capacitive load, its turn-on time and turn-off time are equal, because the circuit is complementary and symmetrical.

The following figure shows when VI=0V, TN is off, TP is on, and the load capacitor CL is charged by VDD through TP. In the CMOS inverter, the gm values of the two transistors are designed to be large, so the on-resistance is small, and the time constant of the charging loop is small. Similarly, we can analyze the discharge process of capacitor CL. The average transmission delay time of CMOS inverters is about 10ns.

Figure 5. Working Speed when vI=0V

3. CMOS Logic Gate Circuit

(1) NAND Gate Circuit

The figure below is a 2-input CMOS NAND gate circuit, which includes two series N-channel enhancement MOSFETs and two parallel P-channel enhancement MOSFETs. Each input terminal is connected to the gate of an N-channel and a P-channel MOSFET.

Figure 5. 2-input CMOS NAND Gate Logic Diagram

When one of the input terminals A and B are low, the NMOS transistor connected to it will be cut off, the PMOS transistor connected to it will be turned on, and output a high level. When both A and B are high level, the two series-connected NMOS transistors are turned on, and the two parallel-connected PMOS transistors are turned off, outputting a low level.

Therefore, this circuit has the logic function of NAND:

The NAND gate of n input terminals must have n series NMOS transistors and n parallel PMOS transistors.

(2) NOR Gate Circuit

The figure below is a 2-input CMOS NOR gate circuit. It includes two parallel N-channel enhancement MOSFETs and two series P-channel enhancement MOSFETs.

Figure 6. 2-input CMOS NOR Gate Circuit

When only one of the input terminal A and B is high, the NMOS transistor connected to it will be turned on, with a low-level output, and the PMOS transistor connected to it will be turned off. When both A and B are low level, the two parallel NMOS transistors are turned off, and the two series PMOS transistors are turned on, and output a high level.

Therefore, this circuit has the logical function of NOR, and its logical expression is:

Similarly, NOR gates with n input terminals must have n parallel NMOS transistors and n parallel PMOS transistors.

Comparing CMOS NAND gates and NOR gates, we can see that the working transistors of the NAND gate are connected in series with each other, and their output voltage increases with the increase of the number of transistors. On the contrary, the working transistors of the NOR gate are connected in parallel, and the output voltage is not seriously affected. Therefore NOR gates are used more often.

(3) XOR Gate Circuit

Figure 7. CMOS XOR Gate Circuit

The picture above shows the CMOS XOR circuit. It consists of a first-level NOR gate and a first-level NAND gate. The NOR gate output. And the output L of the NOR gate is the XOR of the input A and B:

Adding an inverter after the XOR gates constitutes an XNOR gate. The logic symbols of the XOR and XNOR gate are shown in the figure below.

Figure 8. Logic gate Symbols of XOR and XNOR Gate

4. BiCMOS Gate Circuit

Bipolar CMOS or BiCMOS has the advantage of the fast speed of bipolar devices and the low power consumption of MOSFET. Therefore, it is valued by users.

(1) BiCMOS Inverter

Figure 9.Basic BiCMOS Inverter Circuit

The above figure shows the basic BiCMOS inverter circuit. For clarity, the MOSFET is represented by M, and BJT is represented by T.

T1 and T2 constitute a push-pull output stage. The input stage composed of Mp, MN, M1, and M2, similar to the basic CMOS inverter. The input signal VI acts on the gates of MP and MN at the same time. When VI is a high voltage, MN is turned on and MP is turned off; when VI is a low voltage, MP is turned on and MN is turned off.

When the output terminal is connected with a BiCMOS gate circuit, the output stage can provide enough current to charge the capacitive load. In the same way, the charged capacitive load can quickly discharge through T2.

The charge stored in the base area of T1 and T2 can also be released through M1 and M2, to speed up the switching speed of the circuit. When VI is a high voltage, M1 is turned on, and the charge in the base area of T1 is quickly dissipated. This is similar to T1 in the input stage of the TTL gate. When VI is a low voltage, VDD turns on M2 through MP, and the charge in the base area of T2 is dissipated through M2.

Therefore, the switching speed of the gate circuit can be improved.

(2) BiCMOS Gate Circuits

According to the structure and working principle of the CMOS gate circuit mentioned above, NOR gates and NAND gates can also be realized with BiCMOS technology.

To realize the NOR logic relationship, we should use the input signal to drive parallel N-channel MOSFETs, while P-channel MOSFETs are connected in series with each other, as the 2-input NOR gate circuit shown below.

Figure 10. 2-input NOR Gate Circuit

When both A and B are low levels, MOSFETs MPA and MPB are both turned on. T1 is turned on and MNA and MNB are both turned off, and the output L is high. At the same time, M1 is stimulated by VDD through MPA and MPB, thereby providing a release path for the charge in the base area of T2.

On the other hand, when one of the two input terminals A and B is high, the path of MPA and MPB is disconnected, and MNA or MNB is turned on, with a low-level output. Meanwhile, M1A or M1B provides a release path for the charge of the T1 base. Therefore, as long as there is an input terminal connected to a high level, the output is low.

5. CMOS Transmission Gate

The output characteristics of MOSFETs are linearly symmetrical near the origin, so they are often used as analog switches. Analog switches are widely used in sample-and-hold circuits, chopper circuits, analog-to-digital, and digital-to-analog conversion circuits.

Figure 11. CMOS Transmission Gate

The transmission gate (TG) is an analog switch that transmits analog signals. It consists of a P-channel and an N-channel enhancement MOSFET in parallel, as shown in the figure above.

TP and TN are symmetrical, and their drain and source are interchangeable. Suppose their turn-on voltage |VT|=2V and the input analog signal can change from -5V to +5V. In order to prevent the PN junction between the substrate and the drain-source being positively biased, the TP substrate is connected to a voltage of +5V, and the TN substrate is connected to a voltage of -5V. The gates of the two transistors C and are controlled by the complementary signal voltages.

The working condition of the transmission gate is:

When the C terminal is connected to -5V, the gate voltage of TN is -5V, and when VI is any value between -5V and +5V, TN is not conductive. Meanwhile, if the gate voltage of TP is +5V, and TP is also not conductive. So when the C terminal is connected to a low voltage, the switch is open.

In order to turn on the switch, the C terminal C' can be connected to +5V. So the gate voltage of TN is +5V, VI is between -5V and +3V, and TN is turned on. At the same time, the voltage of TP is -5V, and TP will be turned on between -3V and +5V.

It can be seen that when VI<-3V, only TN is turned on, and when VI>+3V, only TP is turned on. When VI is in the range of -3V to +3V, both TN and TP are turned on.

The deeper the conduction of one transistor, the less conduction of the other transistor. In other words, when the on-resistance of one transistor decreases, the on-resistance of the other transistor increases. Since the two transistors are connected in parallel, the on-resistance of the switch is approximately a constant. This is the advantage of CMOS transmission.

In normal operation, the on-resistance value of the analog switch is about hundreds of ohms. This value can be ignored when the analog switch connected in series with an operational amplifier whose input impedance is in megohm.